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general description the max6443?ax6452 low-current microprocessor reset circuits feature single or dual manual reset inputs with an extended 6.72s setup period. because of the extended setup period, short switch closures (nuisance resets) are ignored. on all devices, the reset output asserts when any of the monitored supply voltages drops below its specified threshold. the reset output remains asserted for the reset timeout period (210ms typ) after all monitored supplies exceed their reset thresholds. the reset output is one-shot pulse asserted for the reset timeout period (140ms min) when selected manual reset input(s) are held low for an extended setup timeout period of 6.72s. these devices ignore manual reset transitions of less than 6.72s (typ). the max6443?ax6448 are single fixed-voltage ? supervisors. the max6443/max6444 have a single extended manual reset input. the max6445/max6446 have two extended manual reset inputs. the max6447/ max6448 have one extended and one immediate manual reset input. the max6449?ax6452 have one fixed-threshold ? supervisor and one adjustable-threshold ? supervisor. the max6449/max6450 have two delayed manual reset inputs. the max6451/max6452 have one delayed and one immediate manual reset input. the max6443?ax6452 have an active-low reset with push-pull or open-drain output logic options. these devices, offered in small sot packages, are fully guar- anteed over the extended temperature range (-40? to +85?). applications set-top boxes consumer electronics dvd players modems mp3 players industrial equipment automotive medical devices features ? single- or dual-supply voltage monitors ? precision factory-set reset thresholds from 1.6v to 4.6v ? adjustable threshold to monitor voltages down to 0.63v (max6449?ax6452) ? single or dual manual reset inputs with extended 6.72s setup period ? optional short setup time manual reset input (max6447/max6448 and max6451/max6452) ? immune to short voltage transients ? low 6? supply current ? guaranteed valid reset down to v cc = 1.0v ? active-low reset (push-pull or open-drain) outputs ? 140ms (min) reset timeout period ? small sot143 and sot23 packages max6443?ax6452 ? reset circuits with long manual reset setup period ________________________________________________________________ maxim integrated products 1 v cc mr1 reset gnd max6443 max6444 sot143 top view 4 3 1 2 pin configurations ordering information 19-2656; rev 2; 12/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max6443 us_ _l -t -40? to +85? 4 sot143-4 max6444 us_ _l -t -40? to +85? 4 sot143-4 note: the ? _ ?is a placeholder for the threshold voltage level of the devices. a desired threshold level is set by the two-num- ber suffix found in table 1. all devices are available in tape- and-reel only. there is a 2500-piece minimum order increment for standard versions (table 2). sample stock is typically held on standard versions only. nonstandard versions require a minimum order increment of 10,000 pieces. contact factory for availability. devices are available in both leaded and lead-free packaging. specify lead-free by replacing ?t?with ?t?when ordering. pin configurations continued at end of data sheet.
max6443?ax6452 ? reset circuits with long manual reset setup period 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. all voltages referenced to gnd v cc ..........................................................................-0.3v to +6v open-drain reset ..................................................-0.3v to +6v push-pull reset ........................................-0.3v to (v cc + 0.3v) mr1 , mr2, mr2 , rstin ..........................................-0.3v to +6v input current, all pins.......................................................?0ma continuous power dissipation (t a = +70?) 4-pin sot143-4 (derate 4.0mw/? above +70?) .....320mw 5-pin sot23-5 (derate 7.1mw/? above +70?) .......571mw 6-pin sot23-6 (derate 8.7mw/? above +70?) .......696mw operating temperature range .......................... -40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v cc = 1.0v to 5.5v, t a = -40? to +85?, unless otherwise specified. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units operating voltage range v cc 1.0 5.5 v v cc = 5.5v, no load 7 20 v cc supply current i cc v cc = 3.6v, no load 6 16 ? 46 4.50 4.63 4.75 44 4.25 4.38 4.50 31 3.00 3.08 3.15 29 2.85 2.93 3.00 26 2.55 2.63 2.70 23 2.25 2.32 2.38 22 2.12 2.19 2.25 17 1.62 1.67 1.71 v cc reset threshold v th 16 1.52 1.58 1.62 v reset threshold tempco 60 ppm/? reset threshold hysteresis 2 v th mv t a = 0? to +85? 0.615 0.630 0.645 rstin threshold v th-rstin max6449?ax6452 t a = -40? to +85? 0.610 0.650 v rstin threshold hysteresis v hyst max6449?ax6452 2.5 mv rstin input current i rstin max6449?ax6452 -25 +25 na rstin to reset output delay max6449?ax6452, v rstin falling at 1mv/? 15 ? reset timeout period t rp 140 210 280 ms v cc to reset output delay t rd v cc falling at 1mv/? 20 ? mr1 minimum setup period pulse width t mr 4.48 6.72 8.96 s mr1 + mr2 minimum setup period pulse width max6445/max6446/max6449/max6450 4.48 6.72 8.96 s
max6443?ax6452 ? reset circuits with long manual reset setup period _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units mr2 minimum setup period pulse width max6447/max6448/max6451/max6452 1 s mr2 glitch rejection max6447/max6448/max6451/max6452 100 ns mr2 to reset delay max6447/max6448/max6451/max6452 200 ns manual reset timeout period t mrp 140 210 280 ms mr1 to v cc pullup impedance 25 50 75 k ? mr2 to v cc pullup impedance max6445/max6446/max6449/max6450 25 50 75 k ? v cc 1.00v, i sink = 50?, reset asserted 0.3 v cc 1.20v, i sink = 100?, reset asserted 0.3 v cc 2.55v, i sink = 1.2ma, reset asserted 0.3 reset output low (open drain or push-pull) v ol v cc 4.25v, i sink = 3.2ma, reset asserted 0.4 v v cc 1.80v, i source = 200?, reset deasserted 0.8 v cc v cc 3.15v, i source = 500?, reset deasserted 0.8 v cc reset output high (push-pull) v oh v cc 4.75v, i source = 800?, reset deasserted 0.8 v cc v reset open-drain leakage current i lkg reset deasserted 1 a mr1 , mr2 , mr2 input low voltage v il 0.3 v cc v mr1 , mr2 , mr2 input high voltage v ih 0.7 v cc v note 1: devices production tested at +25?. overtemperature limits are guaranteed by design. electrical characteristics (continued) (v cc = 1.0v to 5.5v, t a = -40? to +85?, unless otherwise specified. typical values are at t a = +25?.) (note 1)
max6443?ax6452 ? reset circuits with long manual reset setup period 4 _______________________________________________________________________________________ typical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max6443/52 toc01 supply voltage (v) supply current ( a) 5.0 4.5 3.5 4.0 2.0 2.5 3.0 1.5 1 2 3 4 5 6 7 8 9 0 1.0 5.5 t a = +25 c t a = -40 c t a = +85 c normalized reset timeout period vs. temperature max6443/52 toc02 temperature ( c) normalized timeout period 60 35 10 -15 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0.95 -40 85 maximum transient duration vs. reset threshold overdrive max6443/52 toc03 reset threshold overdrive (mv) transient duration ( s) 800 600 400 200 50 100 150 200 250 0 0 1000 v th = 4.4v reset occurs above the curve normalized v cc reset threshold vs. temperature max6443/52 toc04 temperature ( c) normalized v cc reset threshold 60 35 10 -15 0.98 0.99 1.00 1.01 1.02 1.03 0.97 -40 85 v cc to reset delay vs. temperature max6443/52 toc05 temperature ( c) v cc to reset delay ( s) 60 35 10 -15 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2 23.6 24.0 20.0 -40 85 v cc = falling at 1mv/ s rstin to reset delay vs. temperature (rstin falling) max6443/52 toc06 temperature ( c) rstin to reset delay ( s) 60 35 10 -15 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2 23.6 24.0 20.0 -40 85 rstin falling at 1mv/ s manual reset to reset delay (max6445/max6446/max6449/max6450) max6443/52 toc07 time (1s/div) mr1 (5v/div) mr2 (5v/div) reset (5v/div) v cc = 5v v cc to reset delay max6443/52 toc08 time (100 s/div) v cc (100mv/div) reset (2v/div) v cc = 4.5v v cc = 4.3v v th = 4.392v
max6443?ax6452 ? reset circuits with long manual reset setup period _______________________________________________________________________________________ 5 detailed description reset output the reset output is typically connected to the reset input of a microprocessor (?). a ?? reset input starts or restarts the ? in a known state. the max6443 max6452 ? supervisory circuits provide the reset logic to prevent code-execution errors during power- up, power-down and brownout conditions (see the typical operating circuit ). reset changes from high to low whenever the moni- tored voltages (rstin or v cc ) drop below the reset threshold voltages. once v rstin and v cc exceed their respective reset threshold voltages, reset remains low for the reset timeout period and then goes high. reset is one-shot pulsed whenever selected manual reset inputs are asserted. reset stays asserted for the nor- mal reset timeout period (140ms min). reset is guaranteed to be in the proper output logic state for v cc inputs 1v. for applications requiring valid reset logic when v cc is less than 1v, see the ensuring a valid reset output down to v cc = 0v section. pin description pin max6443 max6444 max6445 max6446 max6447 max6448 max6449 max6450 max6451 max6452 name function 1 2 2 2 2 gnd ground 21111 reset acti ve- low p ush- p ul l or op en- d r ai n outp ut. res et chang es fr om hi g h to l ow w hen v c c or rs tin d r op s b el ow i ts sel ected r eset thr eshol d and r em ai ns l ow for the 210m s r eset ti m eout p er i od after al l m oni tor ed p ow er - sup p l y i np uts exceed thei r sel ected r eset thr eshol d s. res et i s one- shot p ul sed l ow for the r eset ti m eout p er i od ( 140m s m i n) after sel ected m anual r eset i np uts ar e asser ted l ong er than the sp eci fi ed setup p er i od . for the op en- d r ai n outp ut, use a m i ni m um 20k ? p ul l up r esi stor to v c c . 3?? manual reset input, active low. internal 50k ? pullup to v cc. pull mr1 low for the typical input pulse width (6.72s) to one-shot pulse reset for the reset timeout period. ?? mr1 manual reset input, active low. pull both mr1 and mr2 low for the typical input pulse width (6.72s) to one- shot pulse reset for the reset timeout period. 44444v cc v cc voltage input. power supply and input for the primary microprocessor voltage reset monitor. ?? mr2 manual reset input, active low. internal 50k ? pullup to v cc . pull both mr1 and mr2 low for the typical input pulse width (6.72s) to one-shot pulse reset for the reset timeout period. 5 6mr2 manual reset input. pull the mr2 high to immediately one-shot pulse reset for the reset timeout period. 5 5 rstin reset input. high-impedance input to the adjustable reset comparator. connect rstin to the center point of an external resistor-divider to set the threshold of the externally monitored voltage.
max6443?ax6452 ? reset circuits with long manual reset setup period 6 _______________________________________________________________________________________ manual reset input options unlike typical manual reset functions associated with supervisors, each device in the max6443?ax6452 family includes at least one manual reset input, which must be held logic-low for an extended setup period (6.72s typ) before the reset output asserts. when valid manual reset input conditions/setup periods are met, the reset output is one-shot pulse asserted low for a fixed reset timeout period (140ms min). existing front-panel pushbutton switches (i.e., power on/off, channel up/down, or mode select) can be used to drive the manual reset inputs. the extended manual reset setup period prevents nuisance system resets during normal front-panel usage or resulting from inadvertent short-term pushbutton closure. the max6443/max6444, max6447/max6448, and max6451/max6452 include a single manual reset input with extended setup period ( mr1 ). the max6445/ max6446 and max6449/max6450 include two manual reset inputs ( mr1 and mr2 ) with extended setup peri- ods. for dual mr1 , mr2 devices, both inputs must be held low simultaneously for the extended setup period (6.72s typ) before the reset output is pulse asserted. the dual extended setup provides greater protection from nuisance resets. (for example, the user or service technician is informed to simultaneously push both the on/off button and the channel-select button for 6.72s to reset the system.) the max6443?ax6452 reset output is pulse asserted once for the reset timeout period after each valid manual reset input condition. at least one manual reset input must be released (go high) and then be driven low for the extended setup period before reset asserts again. internal timing circuitry debounces low-to-high manual reset logic transitions, so no external circuitry is required. figure 1 illustrates the single manual reset function of the max6443/max6444 single-voltage monitors, and figure 2 represents the dual manual reset function of the max6445/max6446 and max6449/max6450. the max6447/max6448 and max6451/max6452 include both an extended setup period and immediate setup period manual reset inputs. a low-to-high mr2 rising edge transition immediately pulse asserts the reset output for the reset timeout period (140ms min). if the max6447/max6448 and max6451/max6452 mr2 input senses another rising edge before the end of the 140ms timeout period (figure 3), the internal timer clears and begins counting again. if no rising edges are detected within the 210ms timeout period, reset deasserts. the high-to-low transition on mr2 input is internally debounced for 210ms to ensure that there are no false reset assertions when mr2 is dri- ven from high to low (figure 4). the mr2 input can be used for system test purposes or smart-card-detect applications (see the applications information section). adjustable input voltage (rstin) the max6449?ax6452 monitor the voltage on rstin using an adjustable reset threshold set with an external resistor voltage-divider (figure 5). use the following for- mula to calculate the externally monitored voltage (v mon-th ): v mon-th = v th-rstin ? (r1+ r2) / r2 where v mon-th is the desired reset threshold voltage and v th-rstin is the reset input threshold (0.63v). resistors r1 and r2 can have very high values to mini- mize current consumption because of low leakage cur- rents. set r2 to some conveniently high value (250k ? , for example), and calculate r1 based on the desired reset threshold voltage, using the following formula: r1 = r2 ? (v mon-th / v th-rstin - 1) ? reset timeout period 210ms mr1 setup period 6.72s mr1 reset figure 1. max6443/max6444 manual reset timing diagram mr2 reset mr1 6.72s 210ms figure 2. max6445/max6446/max6449/max64450 manual reset timing diagram
max6443?ax6452 ? reset circuits with long manual reset setup period _______________________________________________________________________________________ 7 applications information interrupt before reset to minimize data loss and speed system recovery, many applications interrupt the processor or reset only portions of the system before a processor hard reset is asserted. the extended setup time of the max6443 max6452 manual reset inputs allows the same push- button (connected to both the processor interrupt and the extended mr1 input, as shown in figure 6) to con- trol both the interrupt and hard reset functions. if the pushbutton is closed for less than 6.72s, the processor is only interrupted. if the system still does not respond properly, the pushbutton (or two buttons for the dual manual reset) can be closed for the full extended setup period to hard reset the processor. if desired, connect an led to the reset output to blink off (or on) for the reset timeout period to signify when the pushbutton is closed long enough for a hard reset (the same led might be used as the front-panel power-on display). smart card insertion/removal the max6447/max6448/max6451/max6452 dual manu- al resets are useful in applications in which both an extended and immediate setup periods are needed. figure 7 illustrates the insertion and removal of a smart card. mr1 monitors a front-panel pushbutton. when closed for 6.72s, reset one-shot pulses low for 140ms min. because mr1 is internally pulled to v cc through a 50k ? resistor, the front-panel switch can be connected to mr2 reset t = 210ms t < 210ms counter reset figure 3. max6447/max6448/max6451/max6452 mr2 assertion debouncingtiming diagram mr2 reset 210ms debouncing period 210ms timeout period positive edge no reset output asserted figure 4. max6447/max6448/max6451/max6452 mr2 deassertion debouncing timing diagram max6449 max6451 rstin v cc r1 r2 reset gnd v mon_th = 0.63 x (r1 + r2) / r2 v mon_th v cc figure 5. calculating the monitored threshold voltages max6443 p v cc reset v cc +3.3v nmi led reset mr1 gnd pushbutton switch: close for < 4.48s for system interrupt; close for > 6.72s for system reset figure 6. interrupt before reset application circuit
max6443?ax6452 a microprocessor for general-purpose i/o control. mr2 monitors a switch to detect when a smart card is inserted. when the switch is closed high (card inserted), reset one-shot pulses low for 140ms. mr2 is internally debounced for 210ms to prevent false resets when the smart card is removed. interfacing to other voltages for logic compatibility the open-drain reset output can be used to interface to a ? with other logic levels. as shown in figure 8, the open-drain output can be connected to voltages from 0 to 6v. generally, the pullup resistor connected to the reset connects to the supply voltage that is being monitored at the ic? v cc pin. however, some systems may use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply (figure 8). keep in mind that as the supervisor? v cc decreases toward 1v, so does the ic? ability to sink current at reset . reset is pulled high as v cc decays toward 0. the voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected. ensuring a valid reset down to v cc = 0v (push-pull reset ) when v cc falls below 1v, reset current-sinking capa- bilities decline drastically. the high-impedance cmos- logic inputs connected to reset can drift to undetermined voltages. this presents no problems in most applications, because most ?s and other circuitry do not operate with v cc below 1v. in applications in which reset must be valid down to 0v, add a pulldown resistor between reset and gnd for the push-pull outputs. the resistor sinks any stray leakage currents, holding reset low (figure 9). the value of the pulldown resistor is not critical; 100k ? is large enough not to load reset and small enough to pull reset to ground. the external pulldown cannot be used with the open-drain reset outputs. transient immunity in addition to issuing a reset to the ? during power-up, power-down, and brownout conditions, these supervi- sors are relatively immune to short-duration falling tran- sients (glitches). the graph maximum transient duration vs. reset threshold overdrive in the typical operating characteristics section shows this relationship. ? reset circuits with long manual reset setup period 8 _______________________________________________________________________________________ max6451 p v cc rstin reset digital input i/o supply core supply +3.3v +1.5v reset mr1 mr2 gnd front-panel switch standard p input and 6.72s manual reset delay smart card detect: immediate one-shot when manual reset closes figure 7. max6451/max6452 application circuit max6444 max6446 max6448 max6450 max6452 p reset reset gnd v cc 5v 3.3v 100k ? n figure 8. interfacing to other voltage levels
the area below the curves of the graph is the region in which these devices typically do not generate a reset pulse. this graph was generated using a falling pulse applied to v cc , starting above the actual reset thresh- old (v th ) and ending below it by the magnitude indicat- ed (reset threshold overdrive). as the magnitude of the transient increases (v cc goes further below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc transient that goes 100mv below the reset threshold and lasts 20? or less does not cause a reset pulse to be asserted. max6443?ax6452 ? reset circuits with long manual reset setup period _______________________________________________________________________________________ 9 max6443 max6445 max6447 max6449 max6451 reset v cc v cc gnd 100k ? figure 9. ensuring reset valid to v cc = 0 part no. suffix ( _ _ ) v cc nominal voltage threshold (v) 46 4.625 44 4.375 31 3.075 29 2.925 26 2.625 23 2.313 22 2.188 17 1.665 16 1.575 table 1. reset voltage threshold part top mark part top mark max6443 us16l kafw max6448 uk16l aeer max6443us23l kafx max6448uk23l aees max6443us26l kafy max6448uk26l aeet max6443us29l kafk max6448uk29l aeeu max6443us46l kafz max6448uk46l aeev max6444 us16l kaga max6449 ut16l abel max6444us23l kagb max6449ut23l abnp max6444us26l kagc max6449ut26l abnq max6444us29l kagd max6449ut29l abnr max6444us46l kafl max6449ut46l abns max6445 uk16l aeef max6450 ut16l abem max6445uk23l aeeg max6450ut23l abnx max6445uk26l aeeh max6450ut26l abny max6445uk29l aeei max6450ut29l abnz max6445uk46l aeao max6450ut46l aboa max6446 uk16l aeen max6451 ut16l abnt max6446uk23l aeeo max6451ut23l aben max6446uk26l aeep max6451ut26l abnu max6446uk29l aeap max6451ut29l abnv max6446uk46l aeeq max6451ut46l abnw max6447 uk16l aeej max6452 ut16l abob max6447uk23l aeek max6452ut23l aboc max6447uk26l aeaq max6452ut26l abod max6447uk29l aeel max6452ut29l aboe max6447uk46l aeem max6452ut46l abof table 2. standard versions table chip information transistor count: 1384 process: bicmos
max6443?ax6452 ? reset circuits with long manual reset setup period 10 ______________________________________________________________________________________ ordering information (continued) part temp range pin-package max6445 uk_ _l -t -40? to +85? 5 sot23-5 max6446 uk_ _l -t -40? to +85? 5 sot23-5 max6447 uk_ _l -t -40? to +85? 5 sot23-5 max6448 uk_ _l -t -40? to +85? 5 sot23-5 max6449 ut_ _l -t -40? to +85? 6 sot23-6 max6450 ut_ _l -t -40? to +85? 6 sot23-6 max6451 ut_ _l -t -40? to +85? 6 sot23-6 max6452 ut_ _l -t -40? to +85? 6 sot23-6 note: the ? _ ?is a placeholder for the threshold voltage level of the devices. a desired threshold level is set by the two-num- ber suffix found in table 1. all devices are available in tape- and-reel only. there is a 2500-piece minimum order increment for standard versions (table 2). sample stock is typically held on standard versions only. nonstandard versions require a minimum order increment of 10,000 pieces. contact factory for availability. devices are available in both leaded and lead-free packaging. specify lead-free by replacing ?t?with ?t?when ordering. max6444 p v cc v cc reset mr1 +3.3v reset gnd gnd reset timeout period 210ms mr1 setup period 6.72s mr1 reset typical operating circuit top view gnd v cc mr1 15 mr2 reset max6445 max6446 sot23-5 2 34 gnd v cc mr1 15 mr2 reset max6447 max6448 sot23-5 2 34 gnd v cc mr1 16 mr2 5 rstin reset max6449 max6450 sot23-6 2 34 gnd v cc mr1 16 mr2 5 rstin reset max6451 max6452 sot23-6 2 34 pin configurations (continued)
max6443?ax6452 ? reset circuits with long manual reset setup period ______________________________________________________________________________________ 11 * other timing options may be available. contact factory for availability. part mr1 setup mr2 (no setup) mr2 setup rstin push-pull reset open-drain reset max6443 6.72s ? max6444 6.72s ? max6445 6.72s 6.72s ? max6446 6.72s 6.72s ? max6447 6.72s ? ? max6448 6.72s ? ? max6449 6.72s 6.72s ?? max6450 6.72s 6.72s ? ? max6451 6.72s ? ?? max6452 6.72s ? ? ? selector guide max6443 max6452 max6449 max6452 max6447 max6448 max6451 max6452 max6445 max6446 max6449 max6450 rstin v cc reset timeout period (210ms typ) mr2 one-shot debounce circuit manual reset setup period (6.72s typ) 0.63v 1.23v mr1 gnd v cc v cc v cc reset mr2 mr2 functional diagram
max6443?ax6452 ? reset circuits with long manual reset setup period 12 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) sot-143 4l.eps e 1 1 21-0052 package outline, sot-143, 4l sot-23 5l .eps e 1 1 21-0057 package outline, sot-23, 5l
max6443?ax6452 ? reset circuits with long manual reset setup period maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 6lsot.eps package outline, sot 6l body 21-0058 1 1 g

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